1. Field of the Invention
The present invention relates to a display device such as a TFT (Thin Film Transistor) liquid crystal display device, a simple matrix liquid crystal display device, an electroluminescence (EL) display device, or a plasma display device, and also to a signal driver of the display device.
2. Description of Related Art
Growth in size of a flat display device such as a liquid crystal television has raised growing demands for a higher-resolution display and a more smooth motion expression. To satisfy these demands, video data with broader bandwidth is required, thus promoting clock speed-up for the display device. However, the clock speed up, an effect of the growth in the size of the display device on power, and an effect of deteriorated ground impedance have caused concern about EMI (Electromagnetic Interference).
Referring to FIGS. 1 and 2, an effect of the EMI will be described.
Typically, a D-A converter 16 in a signal driver 101 has a high output impedance and cannot directly drive a display panel 3. That is, the D-A converter 16 has a low output current capability. Thus, an output amplifier circuit 17 (output buffer) with a high output current capability is used as an output circuit of the signal driver 101. As a result, the signal driver 101, via the output amplifier circuit 17, can output video data (output voltages) to signal lines. However, due to the high output current capability of the output amplifier circuit 17, when a level of a signal indicating video data is inverted from high to low or from low to high, transient currents (peak currents) instantaneously flow into signal lines. Due to the simultaneous inversions of the signals indicating the video data, the simultaneous flows of the peak currents into the signal lines causes large noise. This noise needs to be reduced.
Known as a technique related to the reduction of EMI is a “Liquid crystal display device driving method and driving device” described in Japanese Laid-Open Patent Application JP-A-Heisei 11-259050 (corresponding to U.S. Pat. No. 6,980,192B1). In the technique described in this application, noise generated when display data is transferred from a timing controller 4 to source drivers (signal drivers 101) is reduced. To achieve this, n delay circuits are provided in the timing controller 4, wherein the n delay circuits output n pieces of display data to the n signal drivers 101 at timings respectively, each timing is shifted from the previous timing by a predetermined time interval.
Also known as the technique related to the reduction of EMI is a “Noise reduction circuit of semiconductor device” described in Japanese Laid-Open Patent Application JP-P2003-008424A. In the technique described in this application, the semiconductor device is used as a liquid crystal display data control circuit (signal drivers 101 above), reducing noise generated when outputs of the signal drivers 101 are transferred. To achieve this, noise reduction circuits as delay circuits are provided in the signal drivers 101, wherein the noise reduction circuits output their outputs at timings respectively, each timing is shifted from the adjacent timing by a predetermined time interval.
We have now discovered the following facts. As described above, in the technique described in JP-A-Heisei 11-259050, as the transfer of the display data from the timing controller 4 to the signal drivers 101, the n delay circuits in the timing controller 4 output the n pieces of display data to the n signal drivers 101 at timings respectively, each timing is shifted from the adjacent timing by a predetermined time interval. However, in a recent display device, using a small amplitude differential signal based on the aforementioned LVDS (low voltage differential signaling) has become more common in the data transfer from the timing controller 4 to the signal drivers 101. With such a data transfer method, an output buffer in the timing controller 4 operates at constant current, and thus an excessive peak current is not generated in a current consumed at the output buffer. That is, then delay circuits in the timing controller 4 do not have to output the n pieces of display data to the n signal drivers 101 at timings respectively, each timing is shifted from the adjacent timing by a predetermined time interval. Thus, the technique described in JP-A-Heisei 11-259050 fails to handle excessive current and the reduction of EMI in the recent display devices.
Moreover, in the technique described in JP-A-Heisei 11-259050, as a delay time, time shorter than a video data transfer clock is required. In the case where the small amplitude differential signal based on the LVDS is adopted between the timing controller 4 and the signal drivers 101, the timing controller 4 usually serializes the video data as the display data and outputs it to the signal drivers 101. Thus, a frequency of the output from the timing controller 4 is several hundreds mega hertz, which is very high. A delay control with this high frequency is assumed to lead to cost increase (for the purpose of high accuracy and widening an adjustment range, timing generation by use of PLL (Phase Locked Loop) or the like is required) or is assumed to result in failure to sufficiently reduce the peak current due to a narrow adjustment range.
As described above, in the technique described in JP-P2003-008424A, the semiconductor device is used as the signal driver 101, and as the transfer of the outputs of the signal drivers 101, the noise reduction circuits in the signal drivers 101 output their outputs at timings respectively, each timing is shifted from the adjacent timing by a predetermined time interval. However, no clear description is provided concerning what the outputs of the noise reduction circuits are, what are output destinations of the noise reduction circuits, and between what the noise reduction circuits are connected. Thus, it is difficult to fully review the technique described in JP-P2003-8424A but there is still room for further improvement of this technique.
Thus, the noise generated when the signal drivers 101 transfer the video data to the display panel 3 is desired to be kept lower than conventional one.